At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.
Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.
Centaur opted for a superwide SIMD engine in an accelerator for a multicore x86 aimed at edge server applications that could take full advantage of spare die area.
A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
Mentor has introduced a DFT-automation methodology that is designed to support the growing use of hierarchical strategies.
Accellera to look at interoperability standard for failure analysis tools in safety engineering.
The ESD Alliance is adding design and transportation-systems streams to the Semicon Europa 2019 show.
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