SoC

March 19, 2020

Deploying pre- and post-silicon verification and test for 5G designs

A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
January 10, 2020

MRAM pushes speed and endurance at IEDM

IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: , , ,
November 11, 2019

Mentor takes DFT planning to a higher level for hierarchical flows

Mentor has introduced a DFT-automation methodology that is designed to support the growing use of hierarchical strategies.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
November 8, 2019

Accellera sets up to group to look at interoperability for safety analysis

Accellera to look at interoperability standard for failure analysis tools in safety engineering.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
October 22, 2019

Semicon Europa adds design and smart-transportation seminars

The ESD Alliance is adding design and transportation-systems streams to the Semicon Europa 2019 show.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , , ,   |  Organizations:
May 28, 2019

ARM adds Cortex-A77 and Mali-G77 cores for 5G and ML

The company is also bundling its new CPU and GPU cores in a premium IP platform that can be tuned for next generation applications and devices.
Article  |  Topics: Blog Topics  |  Tags: , , , , , , , , , , , ,   |  Organizations: ,
December 6, 2018

Microchip opts for RISC-V cores in SoC FPGA

Microsemi has put multiple RISC-V cores into a new generation of SoC FPGAs, intended for embedded systems that need to run Linux.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations: ,
November 7, 2018

Symphony raises crescendo for AMS simulation

Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
October 17, 2018

UltraSoC combines tools for cross-SoC debug and analysis

Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:
June 20, 2017

Siemens sees Mentor helping to build fast digital twins

An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.
Article  |  Topics: Blog - EDA, Electrical Design, Embedded, PCB  |  Tags: , , , , , , , ,   |  Organizations: ,

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