AMD moves gradually into 3D integration
At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.
SoC
DAC 2021 preview: Breker Verification Systems
Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
Chiplet design raises big questions
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
Mentor to use UltraSoC acquisition to drive in-life learning
Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.
Ultrawide neural engine fills a hole
Centaur opted for a superwide SIMD engine in an accelerator for a multicore x86 aimed at edge server applications that could take full advantage of spare die area.
Deploying pre- and post-silicon verification and test for 5G designs
A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
MRAM pushes speed and endurance at IEDM
IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
Mentor takes DFT planning to a higher level for hierarchical flows
Mentor has introduced a DFT-automation methodology that is designed to support the growing use of hierarchical strategies.
Accellera sets up to group to look at interoperability for safety analysis
Accellera to look at interoperability standard for failure analysis tools in safety engineering.
Semicon Europa adds design and smart-transportation seminars
The ESD Alliance is adding design and transportation-systems streams to the Semicon Europa 2019 show.