Mentor has introduced a DFT-automation methodology that is designed to support the growing use of hierarchical strategies.
Accellera to look at interoperability standard for failure analysis tools in safety engineering.
The ESD Alliance is adding design and transportation-systems streams to the Semicon Europa 2019 show.
The company is also bundling its new CPU and GPU cores in a premium IP platform that can be tuned for next generation applications and devices.
Microsemi has put multiple RISC-V cores into a new generation of SoC FPGAs, intended for embedded systems that need to run Linux.
Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.
ARM has expanded its DesignStart program by providing access to the Cortex-M3 as well as the M0 with no up-front licence fee.
Former Cadence CEO tells DAC the IoT will lead to a burgeoning of chip design starts, followed by a brutal consolidation.
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