Questa

Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.

Japanese giant uses variable thermal simulation on automotive IC intended for harsh environments.

Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.

About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.

Mentor Graphics chairman and CEO Wally Rhines will deliver the DVCon keynote as the vendor sets a deep agenda for the conference.

New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.

Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.