low power

5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.

A DVCon technical paper addresses potential reset domain crossing metastability issues due to UPF instrumentation.

SureCore has started running 30-day trials of its low-power memory compiler.

The Bangalore conference has issued a last-minute call for panel proposals as technical paper submissions for the US edition get set to open next week.

Power analysis specialist will showcase the 2.0 edition of its PowerBaum analysis and modeling suite at DAC.

The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.

Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.

The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).

L-5 autonomous vehicles need centralized raw data analysis with machine learning to cope with the demands of ASIL-D functional safety. Mentor's response is DRS360.

Implementation uses dedicated PULP technology in silicon for Green Waves Technologies on TSMC's 55nm LP process.