Parasitic extraction challenges intensify for 5G
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
low power
Overcome reset domain crossing challenges when using UPF
A DVCon technical paper addresses potential reset domain crossing metastability issues due to UPF instrumentation.
SureCore provides 30-day test for SRAM compiler
SureCore has started running 30-day trials of its low-power memory compiler.
DVCon US and India chapters issue calls for submissions
The Bangalore conference has issued a last-minute call for panel proposals as technical paper submissions for the US edition get set to open next week.
DAC 2018 preview: Baum
Power analysis specialist will showcase the 2.0 edition of its PowerBaum analysis and modeling suite at DAC.
DVCon US 2018 preview: Mentor
The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.
Arm TechCon 2017 preview: Mentor
Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
DVCon China looms as submission deadline for Europe approaches
The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
Leverage AI and centralized processing for L-5 autonomous vehicles
L-5 autonomous vehicles need centralized raw data analysis with machine learning to cope with the demands of ASIL-D functional safety. Mentor's response is DRS360.
Open-Silicon claims RISC-V ultra-low-power first
Implementation uses dedicated PULP technology in silicon for Green Waves Technologies on TSMC's 55nm LP process.