Expert Insights

Pranav Ashar  |  April 16, 2014

Reset optimization pays big dividends before simulation

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Randall Myers  |  April 8, 2014

Straighten up and fly right

Fighter pilots have long trusted highly sophisticated automation. That’s how you can meet the challenges posed by advanced PCB design techniques.
Joe Kwan  |  April 3, 2014

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
Julian Coates  |  March 27, 2014

Make best-practice lean NPI for PCB a reality

Shifting DFM validation earlier in the flow speeds NPI, cuts respins and gives you a critical edge.
Topics: PCB Topics, PCB - System Codesign  |  Tags: , , , ,   |  Organizations:   |  
Chris Tice  |  March 17, 2014

The rise of hardware-assisted verification

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  
Richard Goering  |  March 6, 2014

Henny Youngman’s advice to PCB designers

In a standing-room-only talk at the recent DesignCon conference, Eric Bogatin explained why comedian Henny Youngman could help them with signal integrity on PCBs.
Topics: PCB - Design Integrity  |  Tags: , ,   |  Organizations:   |  
Warren Stapleton  |  February 27, 2014

Next wave of innovation in verification technology must come from integration

The next boost to verification productivity will come from the integration of multiple strategies and tools.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Lisa Piper  |  February 26, 2014

Complexity drives smart reporting

Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.
Mark Bollar  |  February 11, 2014

The new landscape of advanced design

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.
Sudhakar Jilla  |  February 6, 2014

Concurrency tackles MCMM issues head-on

The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
Topics: EDA - IC Implementation, Verification  |  Tags: ,   |  Organizations:   |  

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