Expert Insights

Luke Collins  |  July 20, 2014

Rethinking SoC verification

The argument for an integrated approach to SoC verification
Pranav Ashar  |  July 3, 2014

It’s time to embrace objective-driven verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
Mick Posner  |  May 24, 2014

Prototypers get faster route to first clock tick

ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Bill Neifert  |  May 15, 2014

Bringing true power analysis to hardware/software co-design

While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging
John Ferguson  |  April 28, 2014

Protecting IP in a collaborative signoff environment

The encryption chain for today's highly collaborative designs needs to be managed with care.
Pranav Ashar  |  April 16, 2014

Reset optimization pays big dividends before simulation

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Randall Myers  |  April 8, 2014

Straighten up and fly right

Fighter pilots have long trusted highly sophisticated automation. That’s how you can meet the challenges posed by advanced PCB design techniques.
Joe Kwan  |  April 3, 2014

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
Julian Coates  |  March 27, 2014

Make best-practice lean NPI for PCB a reality

Shifting DFM validation earlier in the flow speeds NPI, cuts respins and gives you a critical edge.
Chris Tice  |  March 17, 2014

The rise of hardware-assisted verification

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  

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