Expert Insights

Prasad Saggurti  |  August 27, 2014

Six key criteria for deciding to migrate to a finFET process

Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Topics: EDA - IC Implementation, IP - Selection  |  Tags: , ,   |  Organizations: , , , , ,   |  
Joe Kwan  |  August 12, 2014

Sign-off lithography simulation and multi-patterning must play well together

Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
Hitendra Divecha  |  August 7, 2014

Dealing with parasitic-extraction challenges in finFETs and advanced nodes

FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:   |  
Steve Cline  |  July 25, 2014

Using standardized design flows to cut time to tape-out – and speed design-flow evolution

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Rebecca Lipon  |  July 20, 2014

Rethinking SoC verification

The argument for an integrated approach to SoC verification
Pranav Ashar  |  July 3, 2014

It’s time to embrace objective-driven verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
Mick Posner  |  May 24, 2014

Prototypers get faster route to first clock tick

ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Bill Neifert  |  May 15, 2014

Bringing true power analysis to hardware/software co-design

While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging
John Ferguson  |  April 28, 2014

Protecting IP in a collaborative signoff environment

The encryption chain for today's highly collaborative designs needs to be managed with care.
Pranav Ashar  |  April 16, 2014

Reset optimization pays big dividends before simulation

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  

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