The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Forty six companies have joined the consortium developing the increasingly important IPC-2581 data transfer standard for PCB designs.
Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
If you're going to be working on any aspect of multicore embedded system design, a newly published book titled "Real World Multicore Embedded Systems" will be an excellent guide.
What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
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