Understanding design trade-offs can help achieve the correct balance of functionality, cost, and time to market, says design consultancy chief
Constraints are a vital part of IC design, yet the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.
A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
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FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
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