Expert Insights

Dunstan Power  |  January 27, 2015

Assessing technical design trade-offs during product development

Understanding design trade-offs can help achieve the correct balance of functionality, cost, and time to market, says design consultancy chief
Sarath Kirihennedige  |  January 13, 2015

Taking control of constraints verification

Constraints are a vital part of IC design, yet the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.
Topics: Uncategorized  |  Tags: , , , ,   |  Organizations:   |  
Ron Lowman  |  January 7, 2015

A holistic approach to IoT chip design

A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
Lauro Rizzatti  |  November 6, 2014

The budget case for emulation

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
Yervant Zorian  |  October 10, 2014

Finding and fixing faults in finFET memories

FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
Topics: IP - Assembly & Integration, EDA - DFT  |  Tags: , , , ,   |  Organizations:   |  
Pranav Ashar  |  September 30, 2014

The evolution of lint

Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
John Ferguson  |  September 10, 2014

If we’d only known then what we know now

Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.
Topics: EDA - DFM, Verification  |  Tags: , , , ,   |  Organizations:   |  
Prasad Saggurti  |  August 27, 2014

Six key criteria for deciding to migrate to a finFET process

Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Topics: EDA - IC Implementation, IP - Selection  |  Tags: , ,   |  Organizations: , , , , ,   |  
Joe Kwan  |  August 12, 2014

Sign-off lithography simulation and multi-patterning must play well together

Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
Hitendra Divecha  |  August 7, 2014

Dealing with parasitic-extraction challenges in finFETs and advanced nodes

FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:   |  

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