Expert Insights

Pedro Ricardo Miguel  |  August 7, 2017

Supporting higher-resolution displays without major system redesign

Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
Topics: Embedded - Architecture & Design, IP - Assembly & Integration  |  Tags: , , , , ,   |  Organizations: , ,   |  
Ashish Darbari  |  July 21, 2017

Doc Formal: The evolution of formal verification – Part One

Doc Formal begins a two-part series by describing the solid and well-established foundations of formal verification.
Richard Solomon  |  July 18, 2017

Using CCIX to implement cache coherent heterogeneous multiprocessor systems

CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
Gordon Cooper  |  June 29, 2017

High-resolution visual recognition needs high-performance CNNs

Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.
Dana Neustadter  |  June 16, 2017

Protecting content transmitted over USB Type-C connections

SoC developers who want to use USB Type-C in their designs will have to implement HDCP 2.2 content protection so that the target devices will be able to play protected content.
Topics: IP - Selection  |  Tags: , ,   |  Organizations:   |  
John Wilson and Karim Segond  |  June 13, 2017

Cooling power electronics at room level

German consultancy E-Cooling describes its strategy for thermal and airflow analysis.
Topics: Thermal design  |  Tags: , , ,   |  Organizations: , ,   |  
Michael Thompson  |  May 24, 2017

Building processors to enable intuitive human-machine interaction

The increasing complexity of human-machine interfaces is challenging processor designers to produce the necessary performance within a limited power budget
Topics: IP - Selection  |  Tags: , , ,   |  Organizations:   |  
Ashish Darbari  |  May 22, 2017

Introducing Doc Formal: the journey so far

Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
Paul Dempsey  |  May 15, 2017

The Wally Rhines interview – Part Two: AI, automotive and security

This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
John Swanson  |  May 9, 2017

Building faster data centers with 25G Ethernet

The rising bandwidth demands of data centres have driven the development of 25G Ethernet, which will also form a pathway to 100G.
Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , ,   |  Organizations: ,   |  

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors