GaN power makes progress at IEDM 2015
Researchers describe at IEDM 2015 how they are making gallium nitride fit into a wider range of power-handling applications and may even result in mass-market vertical transistors.
EDA
IEDM keynote: cost scaling will swap architectural changes for area
According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.
Cadence partners for photonic IC design
Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.
Three key ways to reduce silicon test costs
Mentor's Greg Aldrich describes how test's market leader is driving down cost in the billion-gate era by rethinking and extending existing technologies
Cadence shifts emulation to the data center
Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
DVCon Europe: UVM-SystemC backers ready first draft
But the bridge standard's European backers still need greater support from the big EDA vendors.
DVCon Europe: Getting TLM to cope with proliferating ECUs and serial protocols
High powered alliance develops TLM standards to address growing automotive and IoT concerns.
ARM snaps up Carbon model IP for prototyping
ARM has moved back into system-level modelling with the decision to buy the tools and models developed by Carbon Design Systems
Mentor targets next-gen Ethernet with emulation
Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.
Mentor’s Wally Rhines on M&A ‘merger mania’
...and why the semiconductor industry hasn't been singularitied down to one MegaSemis Inc even if that's what M&A data suggests.