Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
Webinar explores the impact of ISO 26262 on DFT requirements, and what is being learnt from the introduction of the standard at ON Semiconductor.
Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
Mentor Graphics is looking to get yet more efficiency from its market-leading Veloce emulator family through an OS upgrade and new task-specific Apps.
Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.
National Instruments plans to build an ecosystem around semiconductor test that could provide a missing link between the design process and production.
SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
View All Sponsors