DFT

November 12, 2019

Mentor cuts scan time in package of test measures for automotive designs

Aimed at automotive designs, Mentor has developed a BIST technology that the company claims can speed up the process ten-fold by making more of each scan cycle.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
November 11, 2019

Mentor takes DFT planning to a higher level for hierarchical flows

Mentor has introduced a DFT-automation methodology that is designed to support the growing use of hierarchical strategies.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
April 16, 2019

Boost your DFT efficiency for AI silicon design

Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
Article  |  Topics: Blog Topics, Tested Component to System  |  Tags: , , , , , ,   |  Organizations:
July 3, 2018

Fusion improves timing say Synopsys users

Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
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February 27, 2017

Cadence tunes up simulators and FPGA prototyping

Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
September 14, 2016

Event: How ISO 26262 is driving automotive DFT requirements

Webinar explores the impact of ISO 26262 on DFT requirements, and what is being learnt from the introduction of the standard at ON Semiconductor.
June 10, 2016

DFT to expand its role for long-term yield

Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
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February 25, 2016

Mentor’s Veloce boasts emulation gains fueled by software

Mentor Graphics is looking to get yet more efficiency from its market-leading Veloce emulator family through an OS upgrade and new task-specific Apps.
February 2, 2016

Cadence boosts compression with physical DFT tool

Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
August 7, 2014

NI aims to bring design and production closer with chip-test plan

National Instruments plans to build an ecosystem around semiconductor test that could provide a missing link between the design process and production.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,

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