DAC returns to SF for in-person event
DAC returns to San Francisco in July for its 59th year as a purely in-person event.
DFT
Real Intent tries to shift left on DFT
Real Intent has launched a DFT tool intended to relax the bottlenecks that occur as an SoC project moves into its final phase ahead of tapeout.
Mentor cuts scan time in package of test measures for automotive designs
Aimed at automotive designs, Mentor has developed a BIST technology that the company claims can speed up the process ten-fold by making more of each scan cycle.
Mentor takes DFT planning to a higher level for hierarchical flows
Mentor has introduced a DFT-automation methodology that is designed to support the growing use of hierarchical strategies.
Boost your DFT efficiency for AI silicon design
Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
Fusion improves timing say Synopsys users
Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
Cadence tunes up simulators and FPGA prototyping
Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
Event: How ISO 26262 is driving automotive DFT requirements
Webinar explores the impact of ISO 26262 on DFT requirements, and what is being learnt from the introduction of the standard at ON Semiconductor.
DFT to expand its role for long-term yield
Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
Mentor’s Veloce boasts emulation gains fueled by software
Mentor Graphics is looking to get yet more efficiency from its market-leading Veloce emulator family through an OS upgrade and new task-specific Apps.
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