Mentor Graphics’ DVCon United States 2016 activities are headlined by a conference keynote from chairman and CEO Wally Rhines. The company is also offering a sponsored luncheon on enterprise verification and will be discussing some of the latest features and functionality for its tools on two separate stands during the exhibition.
This year’s DVCon conference and exhibition takes place from Monday 29th February until Thursday 3rd March at the DoubleTree Hotel in San Jose, CA.
Wally Rhines’ keynote is entitled “Design Verification Challenges: Past, Present and Future” (Tuesday, March 1st, 1.30PM, Oak/Fir). As well as reviewing progress to date in verification innovation, Dr Rhines will also look forward to how the industry can meet emerging requirements in areas such as safety and security.
On Tuesday, March 1st, Mentor is also offering a luncheon session (12.00PM-1.15PM, Pine/Cedar), “Enterprise Verification – Visualize This“. Stephen Bailey, Director of Emerging Technologies, will lead a discussion of Mentor’s Enterprise Verification Platform (EVP) which combines the company’s Questa, Veloce, Visualizer, Catapult and PowerPro tools in a comprehensive solution to today’s increasingly taxing challenges.
Mentor will have two stands at the exhibition with staff available to discuss both the latest combined enhancements to the EVP and to individual tools. The Mentor Graphics DVCon corporate stand is Booth #501 and its popular Verification Academy will be based at Booth #702.
The exhibition section of DVCon runs during early evening and afternoon slots on Monday, February 29th (5.00PM-7.00PM), Tuesday, March 1st (2.30PM-6.00PM) and Wednesday, March 2nd (2.30PM-6.00PM).
In addition to its cornerstone activities, Mentor will be active on both the tutorial and technical paper sides of DVCon.
In addition to nine papers in this year’s DVCon poster session (Tuesday, March 1st, 10.00AM-12.30PM, Gateway Foyer), this year’s Mentor presentations include the following.
Mentor Graphics DVCon Tutorials
Cut your design time in half with higher abstraction (Monday, February 29th, 2.00PM-5.00PM, Oak). Presenters: Bob Condon (Intel), Frederic Doucet (Qualcomm), Peter Frey (Mentor Graphics), Mike Meredith (Cadence Design Systems), Dirk Seynhaeve (Intel).
Advanced validation and functional verification techniques for complex low power SoCs (Thursday, March 3rd, 8.30AM-12.00PM, Donner). Presenters: Gabriel Chidolue (Mentor Graphics), Shantanu Samant (Mentor Graphics), Desinghu PS (ARM).
Back to basics: Doing formal the right way (Thursday, March 3rd, 2:00pm – 5:30pm, Donner). Presenters: Joe Hupcey (Mentor Graphics), Mark Eslinger (Mentor Graphics), Doug Smith (Mentor Graphics).
Mentor Graphics DVCon Technical Papers
Tuesday, March 1st
UPF Generic References: Unleashing the Full Potential, Jitesh Bansal, Mentor Graphics. Paper 3.2, Session 3: Low Power Verification (9:00AM-10:30AM, Monterey/Carmel).
Activity Trend Guided Efficient Approach for Peak Power Estimation Using Emulation, Saurabh Jain, Mentor Graphics. Paper 7.2, Session 7: Effective Emulation (3:00PM-4:30PM, Monterey/Carmel).
Wednesday, March 2nd
Parameters, UVM, Coverage & Emulation – Take Two and Call Me In the Morning, Michael Horn, Mentor Graphics. Paper 8.4, Session 8: UVM Applications – II (10:00AM-12:00PM, Oak).
Verification Patterns – Taking Reuse to the Next Level, Harry Foster, Mentor Graphics. Paper 10.1, Session 10: Verification Processes and Resource Management (10:00AM–12:00PM, Monterey/Carmel).
No RTL Yet? No Problem – UVM Testing a SystemVerilog Fabric Model, Rich Edelman, Mentor Graphics. Paper 11.2, Session 11: UVM Applications – III (3:00PM-4:30PM, Oak).