Keynotes for DVCon Europe announced
DVCon Europe has announced its first two keynote speakers, who will cover the topics of AI and the role of virtualisation in ADAS design and implementation
DVCon Europe
A new methodology addresses the increasing challenge of reset domain crossing
Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.
Master the design and verification of next gen transport: Part Four – emulation
Emulation is already playing a vital role in advanced automotive design within a digital twin environment.
Master the design and verification of next gen transport: Part Three – functional safety
The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow
Master the design and verification of next gen transport: Part Two – high-level synthesis
An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
DVCon US and India chapters issue calls for submissions
The Bangalore conference has issued a last-minute call for panel proposals as technical paper submissions for the US edition get set to open next week.
DVCon China looms as submission deadline for Europe approaches
The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
DVCon Europe to examine role of UVM, SystemC in system-level verification
DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Accellera and Mentor’s Dennis Brophy talks standards targets and DVCon
Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
DVCon Europe: UVM-SystemC backers ready first draft
But the bridge standard's European backers still need greater support from the big EDA vendors.
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