SPIE Advanced Lithography Preview: Mentor Graphics

By TDF Staff |  No Comments  |  Posted: February 11, 2016
Topics/Categories: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , , , , , ,  | Organizations: , , , , , ,

Mentor Graphics will have a typically strong presence at SPIE Advanced Lithography 2016 in San Jose later this month (February 21-25).

The company will present nine oral and nine poster papers during the technical conference at the San Jose Marriott, some where its technical staff are the sole authors and others describing work undertaken with partners such as AMD, GlobalFoundries, Samsung and SMIC (see below for full list).

Mentor will then also be participating during the SPIE Advanced Lithography exhibition at the San Jose Convention Center (Booth #225). The exhibition runs on Tuesday (February 23) and Wednesday (February 24). This year’s featured product on Mentor’s stand will be Calibre RET/MDP.

Mentor Graphics technical papers at SPIE Advanced Lithography

February 23


Directed self-assembly (DSA) compliant correction flow with immersion lithography, joint research with GlobalFoundries. Conference 9777/Session 5, 4.50pm

Ultimate 2D resolution printing with negative-tone development, joint research with IBM Thomas J. Watson Research Center. Joint Conference 9779/Session 7 and Conference 9780/Session 4, 4.50pm.


An automated image-based tool for pupil plane characterization of EUVL tools, joint research with Rochester Institute of Technology.

Source mask optimization using 3D mask and compact resist models, joint research with GlobalFoundries

Source mask optimization study based on latest Nikon immersion scanner, joint research with Fudan University, Shanghai Huali Microelectronics and Nikon.

A novel full chip process window OPC based on matrix retargeting, joint research with SMIC.

February 24


Chronicles of compact lithographic modeling, Conference 9780/Session 5, 8.20am.

Bayesian inference for OPC modeling, joint research with Rochester Institute of Technology, Conference 9780/Session 5, 9.20am.

Multi-layer VEB model: capturing interlayer etch process effects for self-aligned via in multi- patterning process scheme, joint research with GlobalFoundries, Conference 9780/Session 6, 11.40am.


Controlling bridging and pinching with pixel-based mask for inverse lithography.

Advanced DFM application for automated bit-line pattern dummy, joint research with SK Hynix.

Design space exploration for early identification of yield limiting patterns, joint research with SMIC.

Design technology co-optimization for 14/10nm metal1 double patterning layer, joint research with Institute of Microelectronics (China).

An integrated design-to-manufacturing flow for SADP.

February 25


Patterns-based DTCO flow for early estimation of lithographic difficulty using optical image processing techniques, joint research with AMD, Conference 9781/Session 5, 8.30am.

A random approach of test macro generation for early detection of hotspots, joint research with Samsung Electronics, Conference 9781/Session 5, 8.50am.

EUV implementation of model-based assist features in contact patterns, joint research with IBM, Conference 9776/Session 14, 2.10pm

Modeling metrology for calibration of OPC models, Joint Conference 9778/Session 14 and Conference 9781/Session 7, 1.30pm.


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