Unisantis aims to use its vertical transistor design in a novel form of DRAM that could improve density four-fold.
Concerns that the diplomatic stand-off between Seoul and Tokyo could hit the supply chain rose again this weekend as South Korean politicians made a surprise visit to disputed islands.
CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.
Despite the intense R&D going into storage-class and other novel forms of non-volatile memories, flash is set to continue as the bulk memory of choice, Micron executive claims in VLSI Symposia keynote.
About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.
The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.
The wait is over for the latest edition of the International Technology Roadmap for Semiconductors (ITRS).
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