Cadence Design Systems

October 27, 2021

DVCon Europe explores pitfalls and possibilities of AI for verification

In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.
October 7, 2021

Combined database underpins 3DIC design suite

Cadence has built a unified database to support a group of tools to support the planning and implementation of 3DIC designs.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
September 13, 2021

Cadence organizes on-device AI into three families

Cadence has organized its machine-learning platforms into three families intended to cover a wide range of on-device AI applications.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations:
July 22, 2021

Cadence uses reinforcement learning to tune flow

Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
May 21, 2021

Cadence pushes its FastSpice to 32 cores

Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
April 16, 2021

Siemens buys formal start-up OneSpin

The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
April 6, 2021

Cadence updates emulation and prototyping lineup

Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
Article  |  Topics: Blog - EDA  |  Tags: ,   |  Organizations:
February 4, 2021

Pulsic goes freemium with analog-preview tool

Pulsic has adopted the freemium approach with a tool that gives designers of analog circuits previews of how they will be implemented on-chip.
August 17, 2020

Cadence uses machine learning to trim constrained-random runtimes

Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
July 21, 2020

DAC Pavilion focuses on cloud-scaling issues

Talks in the Design-on-Cloud Pavilion at this year’s DAC demonstrated how the question over its usage is not so much whether design could or should migrate to the cloud but how to optimize cost and performance when it’s there.

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