Cadence boosts compression with physical DFT tool

By Chris Edwards |  No Comments  |  Posted: February 2, 2016
Topics/Categories: Blog - EDA  |  Tags: , ,  | Organizations:

Cadence Design Systems has reinvigorated its design-for-test (DFT) offering with a tool that uses links to the company’s implementation suite to try to reduce routing overhead and which incorporates a number of techniques intended to decrease time on the production tester.

Paul Cunningham, Cadence vice president of R&D, said the Modus tool was developed in response to the limits that SoC designers have reached in recent years in the use of compression to trade off test time, die cost and coverage. At the 14nm/16nm node, chipmakers are starting to need more than 100-fold compression in their scan vectors to avoid having to buy many more testers.

Although the Cadence tool incorporates technology to support the insertion of test points to make logic paths more amenable to high levels of scan compression, the company has focused primarily on routing improvements and a mechanism that puts registers in the decompression logic to improve compression ratios.

Cunningham said Modus has its roots in the company’s acquisition of IBM’s DFT technology more than 15 years ago. “The code base that we took for Modus is the code base that originally came from IBM. The whole platform is guided by guys who have been in the industry for 30 years.”

Memorable compression

Cunningham said Modus enables greater levels of compression through the addition of registers in the on-chip decompression logic that give it a certain amount of short-term memory.

“We created a decompressor where the number of values you read in are decoupled from the values that you shift into the scan chains,” Cunningham said. “To do that, we put state into the decompressor.”

The registers in the decompressor allow the creation of wider scan trees from a comparatively small set of scan-in pins. As a result, the compression ratio can be increased towards 400x. The memory-based decompressor can be used in concert with test-point insertion for greater levels of compression.

“They are completely orthogonal,” Cunningham said, but added that the company favoured the memory-oriented approach because it has less potential impact on timing closure. “The main challenge for test-point insertion is what if you insert one on a timing-critical path?”

Grid savings

The physically aware portion of Modus is designed to deal with the problem of scan-routing overhead. Cunningham said traditional approaches to the design of the scan tree tend to lead to routing congestion that can lead to the die size growing by 10 per cent. The team took the XOR spreader circuit structure that decompresses and feeds the input stimuli into the individual scan chains and reworked it so that it could be deployed using a more evenly distributed Manhattan grid structure. That reduces the overall routing impact compared with conventional approaches to XOR spreader design, he claimed.

“There is no more wire-length efficient way to get across a 2D chip than a grid,” Cunningham said. “So why not build an XOR circuit that forms a grid?”

The characteristic look of the grid should make it easy to protect the patents the company has filed on the technique. “We can detect it on-chip, so it’s makes a nicely patentable innovation,” Cunningham added.

A further additions to the Modus test portfolio is support for a shared test access bus for use with memory built-in self-test (MBIST) IP.

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