test compression


June 9, 2020

Real Intent tries to shift left on DFT

Real Intent has launched a DFT tool intended to relax the bottlenecks that occur as an SoC project moves into its final phase ahead of tapeout.
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February 2, 2016

Cadence boosts compression with physical DFT tool

Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.
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December 4, 2015

Three key ways to reduce silicon test costs

Mentor's Greg Aldrich describes how test's market leader is driving down cost in the billion-gate era by rethinking and extending existing technologies
June 30, 2015

Chipmakers see 3x test-pattern saving in embedded-test logic

Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using conventional test generation schemes.
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