Verification specialist Real Intent’s DVCon United States 2016 activities are led by a panel session looking at two of the faster growing areas in EDA: Emulation and Static Verification. This year’s DVCon conference and exhibition takes place from Monday 29th February until Thursday 3rd March at the DoubleTree Hotel in San Jose, CA.
The hour-long panel, “Emulation + Static Verification Will Replace Simulation“, is scheduled for 1.30PM on Wednesday March 2nd in the Oak/Fir room.
EDA veteran Jim Hogan will chair a discussion that includes Real Intent’s CTO Pranav Ashar alongside executives from Google, Imagination Technologies, Dialog Semiconductor and Cavium. They will also be joined by Tech Design Forum contributor and emulation consultant Lauro Rizzatti. A full abstract for the panel appears below.
Real Intent’s booth activities will focus on the latest innovations and use models for the company’s Ascent and Meridian product lines, addressing key challenges in functional verification and advanced sign-off. The company will be found in Booth #802.
The exhibition section of DVCon runs during early evening and afternoon slots on Monday, February 29th (5.00PM-7.00PM), Tuesday, March 1st (2.30PM-6.00PM) and Wednesday, March 2nd (2.30PM-6.00PM).
Real Intent’s DVCon United States panel abstract
Emulation + Static Verification Will Replace Simulation – Wednesday, March 2nd, 1.30PM, Oak/Fir.
Emulation and static verification have both been on a tear lately. With processor frequency at a plateau of few GHz and the “processor + system architecture + software” combine still catching up to the parallelism imperative, emulation has stepped up to fill the void nicely. Almost all chips go through some combination of emulation or FPGA-prototyping prior to product release. With a cloud-based pay-as-you-go model, emulation doesn’t even have to be expensive. Emulation is all about speed – the only way to push through stimuli through a high-end SoC.
Likewise, static verification is also on a steep upward spiral with almost universal adoption of targeted tools for sign-off verification problems like clock domain crossing as well as increasing adoption for problems like power management, reset analysis, X-verification, timing exceptions, security, SOC integration and so on. System-level functional formal verification has been on a slower but also positive adoption trajectory. On verification problems where they work well, static methods have come to deliver enhanced productivity and sign-off level confidence. Static tools ensure that design quality is already extremely high before simulation or emulation is started.
May be the verification paradigm of the future is to invest in high-end targeted static verification tools to get the design to a very high quality level, followed by very high-speed emulation or FPGA-prototyping for system-level functional verification. Where does that leave RTL simulation? Between a rock and a hard place! Gate-level simulation is already marginalized to doing basic sanity checks. Maybe RTL simulation will follow. Or will it?
- Ashish Darbari – Imagination Technologies Ltd.
- Richard Ho – Google, Inc.
- Lauro Rizzatti – Consultant
- Brian Hunter – Cavium, Inc.
- Steven Holloway – Dialog Semiconductor
- Pranav Ashar – Real Intent, Inc.