The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
A technical paper originally presented at DVCon USA 2020 simplifies the creation of coverage strategies using manual, automated and verification IP components.
The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
ES Design West was created to reflect integration, even elision of tasks across the semiconductor supply chain. Here's how the program reflects the trend.
RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.
Popular Verification Academy manual revamped and updated to bring it more closely in line with IEEE 1800.2 UVM and reflect the increasing use of emulation.
The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
Synopsys is targeting artificial intelligence (AI) and data centre SoCs as key application areas for the interface IP.
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