verification IP

April 2, 2019

DVCon China 2019 preview: SmartDV

RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.
Article  |  Topics: Blog - EDA, - Standards, Verification  |  Tags: , , , ,   |  Organizations: ,
March 26, 2019

UVM Cookbook released in new edition

Popular Verification Academy manual revamped and updated to bring it more closely in line with IEEE 1800.2 UVM and reflect the increasing use of emulation.
Article  |  Topics: Blog - EDA, - Standards, Verification  |  Tags: , , , , , ,   |  Organizations:
February 19, 2019

DVCon USA 2019 preview: SmartDV

The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
Article  |  Topics: Conferences, Verification  |  Tags: , , ,   |  Organizations: ,
December 14, 2018

Synopsys announces DDR5 and LPDDR5 interface IP

Synopsys is targeting artificial intelligence (AI) and data centre SoCs as key application areas for the interface IP.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations: , , ,
May 3, 2017

Master the verification challenge of PCIe-based NVMe storage

NVMe is driving the SSD market thanks to its many useful features, but at least five major challenges must inform your verification plan.
Article  |  Topics: Blog - EDA, - Standards, Verification  |  Tags: , , , ,   |  Organizations: ,
February 15, 2017

DVCon US 2017 preview: Mentor Graphics

The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
March 1, 2016

Mentor builds out verification IP for memory

About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.
May 21, 2015

OneSpin uses app-store approach to open up formal verification

Formal-verification specialist OneSpin is setting up its own equivalent of an app store, building on top of a formal engine the company now licenses to other companies.
February 11, 2015

Accellera sets up group for one-stop verification stimulus

Accellera has set up a working group to develop a language-independent way of capturing and managing test stimuli that can be used across a wide range of verification environments.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
April 10, 2014

Mentor builds simulation-emulation bridge to ‘Verification 3.0’

Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.

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