Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Breker's presence at next week's Design Automation Conference (DAC) will emphasize a new collaboration around the RISC-V platform.
The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
A technical paper originally presented at DVCon USA 2020 simplifies the creation of coverage strategies using manual, automated and verification IP components.
The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
ES Design West was created to reflect integration, even elision of tasks across the semiconductor supply chain. Here's how the program reflects the trend.
RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.
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