DVCon Europe

October 28, 2020

DVCon keynoters look to software for verification optimization ideas

Speakers at this year's DVCon Europe called on the hardware community to find inspiration in software-development trends.
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October 15, 2020

DVCon Europe: using all the tools at your disposal

Among the papers that will be presented at the end of October, this year's DVCon Europe will demonstrate the benefits of taking good ideas from wherever you can in the pursuit of more effective verification flows.
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October 8, 2020

DVCon Europe brings virtual rooms to online conference

As part of its move online during the pandemic, DVCon Europe is introducing what the organizers call Virtual Experience Rooms.
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July 7, 2020

DVCon Europe goes virtual

The organizers of DVCon Europe have decided to turn the autumn verification conference into a virtual event this year.
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October 29, 2019

Mentor scales AMS cloud verification to 10,000 cores

Tests on Microsoft Azure's cloud have shown Mentor's AMS simulation tools can run across thousands of processors with near-linear scaling.
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October 29, 2019

Circuit analysis speed up radiation checks for automotive SoCs

Optima DA has launched a family of tools designed to speed up the analysis of radiation susceptibility in automotive SoC designs.
October 14, 2019

DVCon Europe looks to software for next phase in verification

October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
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September 5, 2019

DVCon keynotes to look at edge computing and network evolution

DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.
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March 26, 2019

DVCon Europe looks to software in call for papers

DVCon Europe has added embedded software, digital twin, machine learning, and RISC-V to the topics the conference organizers want to cover.
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October 17, 2018

DVCon Europe takes in machine learning and stimulus for verification

Next week's DVCon Europe conference in Munich will tackle a range of topics, from analog verification to the use of machine learning for functional verification, backed up with case studies on the use of TLM and SystemC in live projects.
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