10nm

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.

Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.

EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.

Ceva's latest iteration of its XC architecture aims at the intensive DSP required for 5G basestations.

Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.

STMicroelectronics, Samsung, GSI Technology and Synopsys talk about the challenges of doing AMS design on finFET processes.

Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.

ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.

But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.