June 20, 2022
Intel expects to double logic density through metal scaling and smaller cells with upcoming process.
July 19, 2021
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
May 2, 2021
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
January 15, 2021
The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.
December 18, 2020
Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
November 9, 2020
This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
November 3, 2020
Mentor's latest additions to Tessent aim to cut test time by a factor of four but remains tailored for increasing design complexity.
October 15, 2020
Among the papers that will be presented at the end of October, this year's DVCon Europe will demonstrate the benefits of taking good ideas from wherever you can in the pursuit of more effective verification flows.
May 26, 2020
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
April 30, 2020
Keynotes at this year’s IRPS conference focused on the way in which scaling is forcing changes to the way that the reliability aspects of semiconductors are examined.