layout dependent effects


September 21, 2020

Deliver RFIC reliability and performance through automation

Today's increasingly complex and integrated RFICs pose complex verification challenges best addressed before costly simulation runs.
Article  |  Topics: Verification  |  Tags: , , , , , , ,   |  Organizations:
July 28, 2015

Samsung applies early prediction and color management to 10nm plans

Rapid virtual prototyping and a metal stack that's more designer friendly are two of the ways in which Samsung aims to build up foundry market share for its 14nm and 10nm finFET processes.
October 2, 2013

Old problems on a new scale

For the new web TV program Unhinged, Brian Fuller talked to venture capitalist Jim Hogan about the future of mixed-signal and the past of EDA.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
July 15, 2013

Electrically aware Virtuoso aims to head off physical issues

Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.
January 28, 2013

Cadence updates Virtuoso for the 20nm generation

Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.

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