DVCon Europe: using all the tools at your disposal

By Chris Edwards |  No Comments  |  Posted: October 15, 2020
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , ,  | Organizations: , , ,

Among the papers that will be presented at the end of October, this year’s DVCon Europe will demonstrate the benefits of taking good ideas from wherever you can in the pursuit of more effective verification flows.

Several of the keynotes at the upcoming conference, taking place October 27-28, look at lessons and tools that can be borrowed from the world of software. Though software itself has its issues in terms of code quality problems that would sink the average SoC if translated to hardware design, the rise of the cloud is changing overall productivity by automating laborious processes that can readily be adapted to RTL and system-level verification and bug-hunting. The ability to not just spin up compute nodes that can run prepackaged tests but use scripts to determine when and how to run those tests is already having benefits in more agile flows.

In her conference keynote, Victoria Mitchell, vice president of system engineering at Arm, will describe how these kinds of cloud “devops” can help the hardware engineering team. Similarly, Moshe Zalcberg, CEO of Veriest Solutions, will look at what ideas from the software world can be adapted to silicon and systems engineering.

Tracking issues

One of the issues that continuous integrations flows have to deal with is that design and verification have to be able to move in parallel, which can cause problems when trying to keep track of defects, some of which can be allowed to progress because they will most likely be corrected as the details of the design are filled in. In one highlight paper at Devcon Europe, engineers at CorrectDesigns and Teradyne describe a novel approach for constructing and using an executable defect table to track and work around open issues as a design progresses. The defect table provides a place for information on “to dos” to be stored and prevent tools from flagging them as important until they need to be fixed. The authors claim: “It is a powerful technique for projects involving high RTL churn, frequent features/design changes, and/or long turnaround times from the time an RTL issue is found to when it is fixed.”

Cross-pollination is possible at all levels. In the conference technical sessions, a team from Infineon Technologies and Stanford University will examine how digital technology in the form of FPGAs can accelerate analog and mixed-signal design. The team has applied an open-source modeling framework to generate synthesizable functional models of analog behavior that run at high speed on Xilinx FPGAs using abstract model specifications. By bringing high-speed mixed-signal emulation into the flow, the models can support applications such as hardware-in-the-loop verification: a key element of automotive engineering among others.

In the paper, the team uses FPGA emulation to model the behavior of magnetic sensors to detect the speed and rotational angle of moving parts in wheels, steering systems, and engine parts. The modeling is used to help improve the effective resolution that can be measured by these sensors and deal with problems such as stray field detection.

SystemC learns about time

In another example of ideas being pulled into new environments to suit the general shift-left trend, a team from Intel will describe at the conference a proposed set of assertions for SystemC that support temporal modeling and checking. The assertions are similar to those used in SystemVerilog but allow high-level system models to capture information and requirements for situations where a timely response to stimulus is crucial. Compatibility with the SystemVerilog set allows for the possibility to have the assertions translated to SVA during high-level synthesis and so preserve requirements as the design progresses.

Another approach to making sure information captured early makes it through the flow can be found in a paper from a team working at Robert Bosch and the University of Tübingen. This focuses on the use of the SysML language for hardware and system modeling to develop design and assertion information that can be transferred into the SystemVerilog domain to support RTL creation and verification. According to the authors, “the contribution enables a semi-formal description of the specification in tabular form” to reduce ambiguity and support validation of the specification.

The conference also sees numerous applications of formal technologies for detecting deadlocks and building and checking reset networks among other applications, demonstrating how many different types of tool need to come together to support modern verification flows.

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