Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.
Cadence has built a unified database to support a group of tools to support the planning and implementation of 3DIC designs.
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.
Glass may be the high frequency interposer option given silicon concerns about power and noise. TSMC adds another pathfinder to its 3D arsenal.
TSMC stays the course with new co-CEOs as Morris Chang retains executive leadership for now while finFET, 3D and other new technologies settle in.
Research projects to verify methodologies, address third-party integration challenges and add a low-cost interposer-like technology to the 3D-IC family make their mark.
Stacked 3D-IC memory-on-logic is on the packaging company's roadmap, but there are still yield hurdles to scale at the MEOL.
3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
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