reliability analysis


January 28, 2020

Earlier latch-up prevention with topology-based analysis

By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
November 17, 2015

Performance and timeout checks added to on-chip network

Sonics has add static performance analysis to its SonicsStudio tool and timeout detection to its SonicsGN network intended to prevent SoCs locking up.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
August 28, 2014

Mentor joins European power electronics consortium

Will help industry giants develop more reliable power electronics systems for applications including transport and power generation.
Article  |  Topics: General  |  Tags: , ,   |  Organizations:
May 13, 2014

Mentor targets 10X cut in reliability test for power electronics

New MicReD power tester identifies failure causes without the need for post-test lab analysis
December 18, 2012

DATE conference prepares program for March

In 2013, the Design Automation and Test in Europe (DATE) conference returns to Grenoble, France and with focus days on the Internet of Things and the cloud.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:

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