Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
Tabula expects to have 22nm FPGAs next year and is trying to recruit IP developers to an 'app store' for data-center hardware.
National Instruments wants to shift the focus for many embedded systems designers away from hardware cost optimization towards graphical programming as a way of reducing the time it takes to get targets up, running and productive.
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
Achronix plans to use the FPGA fabric that it has developed for standalone products to be fabbed through Intel as the springboard for an embedded-FPGA offering.
TSMC follows Intel in taking a stake in ASML to accelerate development of EUV and 450mm lithography equipment.
The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.
Intel's Ivy Bridge series of processors were designed from the outset to be split apart and recombined to create variants of the base platform, Intel architecture project manager Brad Heaney explained during the Wednesday keynote session at DAC 2012.
Could more flexible licensing strategies for cloud-based EDA enable more efficient simulation and a new wave of business models?
A startup has analyzed the shape of Intel's fins and found the process is not quite as well-behaved as circuit designers would perhaps like.
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