chiplet

Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.

Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.

The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.

Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.

Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.

Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.

System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.

At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.

University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.

A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.