chiplet


July 28, 2021

Automate latchup verification for 3DIC

A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
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July 19, 2021

Chiplet design raises big questions

Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
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July 15, 2021

Chiplets to need digital twins for reliability

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
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July 8, 2020

Scaling costs tip balance toward chiplets for AMD server processors

In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
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May 21, 2019

Achronix deploys network on chip for faster FPGAs

Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
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April 22, 2019

Machine learning and chiplets headline VLSI Symposia

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
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April 4, 2019

ODSA weighs options for chiplet interconnect

An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
March 18, 2019

PCI may provide key to OCP chiplet standard

The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.
November 6, 2018

Netronome launches chiplet initiative for network-accelerator SIPs

Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
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