Scaling costs tip balance toward chiplets for AMD server processors
In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
chiplet
Achronix deploys network on chip for faster FPGAs
Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
Machine learning and chiplets headline VLSI Symposia
Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
ODSA weighs options for chiplet interconnect
An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
PCI may provide key to OCP chiplet standard
The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.
Netronome launches chiplet initiative for network-accelerator SIPs
Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
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