chiplet

September 27, 2022

Siemens automates test to handle multi-die 2.5D, 3D and 5.5D architectures

Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
Article  |  Topics: EDA - DFT  |  Tags: , , , , , , , , , ,   |  Organizations:
September 21, 2022

Nvidia proposes split-level link for chiplet interconnect

Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations:
September 8, 2022

Module verification demands integrated DRC and LVS

The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
April 28, 2022

Go inside proposals for common chiplet models

Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
March 23, 2022

Nvidia open to chiplet standards

Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
February 10, 2022

Capturing connectivity for assembly verification in 2.5D and 3D design

Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.
Article  |  Topics: Verification  |  Tags: , , , , , , , , ,   |  Organizations:
February 8, 2022

How digital twin evaluations optimize STCO-based design

System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
December 31, 2021

AMD moves gradually into 3D integration

At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmakerā€™s use of chiplet-based design and manufacture.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations:
November 8, 2021

Chiplets may have to prove themselves for secure operation

University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , , ,   |  Organizations:
July 28, 2021

Automate latchup verification for 3DIC

A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

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