Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.
South Korea's leading research institute has built a reusable flow for lower power petaflops-performance AI.
Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.
System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
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