chiplet

April 28, 2022

Go inside proposals for common chiplet models

Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
March 23, 2022

Nvidia open to chiplet standards

Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
February 10, 2022

Capturing connectivity for assembly verification in 2.5D and 3D design

Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.
Article  |  Topics: Verification  |  Tags: , , , , , , , , ,   |  Organizations:
February 8, 2022

How digital twin evaluations optimize STCO-based design

System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
December 31, 2021

AMD moves gradually into 3D integration

At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmakerā€™s use of chiplet-based design and manufacture.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations:
November 8, 2021

Chiplets may have to prove themselves for secure operation

University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , , ,   |  Organizations:
July 28, 2021

Automate latchup verification for 3DIC

A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
July 19, 2021

Chiplet design raises big questions

Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , , ,   |  Organizations: , , ,
July 15, 2021

Chiplets to need digital twins for reliability

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
July 8, 2020

Scaling costs tip balance toward chiplets for AMD server processors

In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations:

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