TCAD


April 30, 2020

Scaling drives targeted analysis of reliability issues

Keynotes at this year’s IRPS conference focused on the way in which scaling is forcing changes to the way that the reliability aspects of semiconductors are examined.
June 8, 2015

DTCO tool aims to squeeze more out of older processes

Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
May 25, 2015

Shape a major choice for sub-10nm nanowire FETs

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
August 19, 2014

Simulations point to better performance for Intel 14nm finFET

Gold Standard Simulations has run simulations to work out how much of an improvement Intel's new rectangular shape represents.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,
July 25, 2014

GlobalFoundries licenses atomistic TCAD simulator toolchain

Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,
July 10, 2014

Startup claims recipe for ultimate finFET

FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

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