debug

August 27, 2019

How to achieve faster, more relevant early-stage DRC with Recon

The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
Article  |  Topics: Digital/analog implementation, Verification  |  Tags: , , , , , , , ,   |  Organizations:
April 3, 2019

DVCon China 2019 preview: Breker Verification Systems

Breker CEO Adnan Hamid will lead a tutorial on the Portable Stimulus Standard as part of the verification specialist's activities in Shanghai.
February 18, 2019

UltraSoC scales up debug architecture

UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
February 11, 2019

DVCon USA 2019 preview: Mentor

DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
October 29, 2018

Mentor extends Tessent for debug and automotive pattern generation

As ITC 2018 begins, Mentor addresses stringent ISO 26262 requirements and looks to bridge the gap in how IJTAG-based debug is structured.
Article  |  Topics: Tested Component to System  |  Tags: , , , ,   |  Organizations: , ,
October 17, 2018

UltraSoC combines tools for cross-SoC debug and analysis

Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:
June 21, 2018

DAC 2018 preview: Real Intent

Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.
Article  |  Topics: Conferences, Blog - EDA, - Verification  |  Tags: , , ,   |  Organizations:
May 22, 2018

Arm Cortex-A processor team focuses on formal

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
May 1, 2018

Andes teams with Imperas and UltrasoC for RISC-V

Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
February 20, 2018

DVCon US 2018 preview: OneSpin Solutions

The formal verification specialist will leverage its recent, successful certification by TÜV SÜD for functional safety solutions.

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