debug

July 30, 2020

Second formal check aids deadlock hunting

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
Article  |  Topics: Verification  |  Tags: , , , ,   |  Organizations: , ,
June 23, 2020

Mentor to use UltraSoC acquisition to drive in-life learning

Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations: ,
February 24, 2020

DVCon US 2020 preview: SmartDV

The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
Article  |  Topics: Blog - IP, - Verification  |  Tags: , , , , , , ,   |  Organizations: ,
December 17, 2019

Automating the pain out of clock domain crossing verification

A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations: ,
December 11, 2019

Support for RISC-V expands at summit

This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
August 27, 2019

How to achieve faster, more relevant early-stage DRC with Recon

The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
Article  |  Topics: Digital/analog implementation, Verification  |  Tags: , , , , , , , ,   |  Organizations:
April 3, 2019

DVCon China 2019 preview: Breker Verification Systems

Breker CEO Adnan Hamid will lead a tutorial on the Portable Stimulus Standard as part of the verification specialist's activities in Shanghai.
February 18, 2019

UltraSoC scales up debug architecture

UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
February 11, 2019

DVCon USA 2019 preview: Mentor

DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
October 29, 2018

Mentor extends Tessent for debug and automotive pattern generation

As ITC 2018 begins, Mentor addresses stringent ISO 26262 requirements and looks to bridge the gap in how IJTAG-based debug is structured.
Article  |  Topics: Tested Component to System  |  Tags: , , , ,   |  Organizations: , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors