Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.
The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.
This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
Breker CEO Adnan Hamid will lead a tutorial on the Portable Stimulus Standard as part of the verification specialist's activities in Shanghai.
UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.
DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
As ITC 2018 begins, Mentor addresses stringent ISO 26262 requirements and looks to bridge the gap in how IJTAG-based debug is structured.
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