debug

The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.

In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.

Virtual strategies make for greater productivity and widen the number of emulation use cases. A new paper considers some of the most popular examples.

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.

Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.

The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.

A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.

This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.

The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.

Breker CEO Adnan Hamid will lead a tutorial on the Portable Stimulus Standard as part of the verification specialist's activities in Shanghai.