process variation


July 8, 2019

Coventor updates process simulation tool

Coventor has updated its SEMulator virtual-fab tool and added the ability to tune process windows based on simulation results.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,
August 16, 2018

IBM and Synopsys to apply DTCO to post-finFET process development

Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.
April 6, 2017

Solido sets up lab to drive machine-learning adoption

Solido aims to bring the types of machine-learning techniques the company has used for its physical-analysis tools to a wider range of EDA tools through the launch of its ML Labs initiative.
February 23, 2016

Directed self assembly may offer similar benefits to EUV, process modeling study says

Directed self assembly techniques may offer similar benefits to EUV lithography, especially for DRAM makers, says SPIE conference paper
Article  |  Topics: Conferences  |  Tags: , , , ,   |  Organizations:
December 7, 2015

Asymmetric variability issues could impact 7nm processes

Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , ,   |  Organizations: , ,

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