bus protocol


October 8, 2019

UltraSoC adds security checks to bus monitoring IP

UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
July 2, 2019

SmartDV adds verification IP for OpenCAPI data-center standard

The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.

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