memory

April 29, 2022

Navigate variables and lifetimes in SystemVerilog

Variable lifetimes are an apparently basic but also tricky feature within the verification language.
Article  |  Topics: Verification  |  Tags: , , , , ,   |  Organizations: ,
April 27, 2022

Verifying the new namespace storage options in NVMe 2.0

The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations:
December 6, 2021

DAC 2021 preview: Breker Verification Systems

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
June 16, 2021

Samsung moves further into 3D for denser flash

Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
May 20, 2021

Denser DRAM looks to flash for inspiration

Unisantis aims to use its vertical transistor design in a novel form of DRAM that could improve density four-fold.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
December 17, 2020

Macronix proposes 3D to breathe life back into NOR flash

At IEDM this year, Macronix showed how a 3D architecture may bring back NOR flash, which stopped scaling a decade ago.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations:
January 24, 2020

SureCore provides 30-day test for SRAM compiler

SureCore has started running 30-day trials of its low-power memory compiler.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations:
September 2, 2019

South Korea-Japan tensions continue to threaten memory supply chain

Concerns that the diplomatic stand-off between Seoul and Tokyo could hit the supply chain rose again this weekend as South Korean politicians made a surprise visit to disputed islands.
August 5, 2019

Flash Memory Summit: Memblaze demos Toshiba ULL NVM technology

The Chinese memory module specialist will preview the 2020 launch of its new solution based on the ultra low latency XL-Flash technology from Toshiba.
Article  |  Topics: Conferences, Blog - Embedded, - Product  |  Tags: , , ,   |  Organizations: ,
July 2, 2019

SmartDV adds verification IP for OpenCAPI data-center standard

The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.

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