Variable lifetimes are an apparently basic but also tricky feature within the verification language.
The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
Unisantis aims to use its vertical transistor design in a novel form of DRAM that could improve density four-fold.
At IEDM this year, Macronix showed how a 3D architecture may bring back NOR flash, which stopped scaling a decade ago.
SureCore has started running 30-day trials of its low-power memory compiler.
Concerns that the diplomatic stand-off between Seoul and Tokyo could hit the supply chain rose again this weekend as South Korean politicians made a surprise visit to disputed islands.
The Chinese memory module specialist will preview the 2020 launch of its new solution based on the ultra low latency XL-Flash technology from Toshiba.
The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
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