Tech Design Forum Briefing


Briefing Authors

Paul Dempsey

Paul Dempsey Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.

Luke Collins

Luke Collins Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.

Chris Edwards

Chris Edwards Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
July 31, 2020

Open-RAN puts more focus on emulation in testing programs

Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.

July 30, 2020

Second formal check aids deadlock hunting

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.

July 29, 2020

Litho hotspot analysis gets machine-learning turbocharge

A Mentor-Samsung collaboration cuts the need for model-based analysis and speeds analysis runtime by as much as 20X.

July 27, 2020

Open and propietary verification tools home in on RISC-V core quality

DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.

July 23, 2020

Accellera IP security group expects standard by year end

The chair of Accellera’s IP security assurance working group expects the draft standard for hardening hardware core to be out by the end of the year.

July 21, 2020

DAC Pavilion focuses on cloud-scaling issues

Talks in the Design-on-Cloud Pavilion at this year’s DAC demonstrated how the question over its usage is not so much whether design could or should migrate to the cloud but how to optimize cost and performance when it’s there.

July 21, 2020

3D integration technologies will blend says TSMC chief scientist

DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday

July 21, 2020

Breker packages up apps for RISC-V, security and AI

Breker has added a number of specialized apps to its library that deal with the verification of RISC-V processors, secure enclaves, and machine-learning designs.

July 20, 2020

FastSPICE upgrade boosts nano-scale analog verification by up to 10X

Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.

July 20, 2020

Mentor tunes LVS for early SoC integration

Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.

Previous Blog Posts

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors