A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
Safety verification calls for increased collaboration across the supply chain, experts say. The challenge is finding ways to make that happen.
The Chinese memory module specialist will preview the 2020 launch of its new solution based on the ultra low latency XL-Flash technology from Toshiba.
Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.
Arm has introduced a licensing model that makes it easier to try out cores during a design before committing to production.
Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
Coventor has updated its SEMulator virtual-fab tool and added the ability to tune process windows based on simulation results.
ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
The Bangalore conference has issued a last-minute call for panel proposals as technical paper submissions for the US edition get set to open next week.
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