Automate latchup verification for 3DIC
A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
ST makes its first 200mm SiC wafers
STMicroelectronics has made its first silicon carbide wafers that can be run on a 200mm line.
Learn how to apply formal verification to safety-critical aviation designs
A detailed technical overview of formal verification within the context of the DO-254 (ED-80) standard is now available to download.
Cadence uses reinforcement learning to tune flow
Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
Arm shows off biggest flex processor so far
Arm and flexible-electronics specialist PragmatIC have demonstrated a 32bit processor implemented on a plastic substrate.
Chiplet design raises big questions
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
How to meet formal embedded software guidance for medical devices
Vulnerabilities in connected healthcare products have led medical requlators to issue further security recommendations for their design and maintenance.
Chiplets to need digital twins for reliability
The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
Accellera approves IP security-documentation standard
Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
From iterative to in-design DRC and debug for place and route
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
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