Tech Design Forum Briefing


Briefing Authors

Paul Dempsey

Paul Dempsey Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.

Luke Collins

Luke Collins Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.

Chris Edwards

Chris Edwards Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
February 22, 2024

Cadence to work on IP for Intel 18A

Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.

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February 8, 2024

Accellera forms working group for mixed-signal interfaces

Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.

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February 1, 2024

Future Facilities core drives Cadence thermal suite

Cadence has introduced a platform for performing thermal and thermal-stress analysis of subsystems, from 2.5D and 3DICs to PCBs and complete electronic assemblies.

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January 21, 2024

Take a deeper dive into BCI-ROM

A new paper looks at examples for using The Boundary Condition Independent Reduced Order Model (BCI-ROM) in its VHDL-AMS implementation for electro-thermal analysis.

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January 12, 2024

DVCon gears up for March in San Jose

Workshops on portable stimulus, functional safety, verification of RISC-V processors, and design with chiplets and large language models will feature at the upcoming 2024 DVCon US.

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December 27, 2023

Flow stability and chip reliability top the papers at DVCon Europe

The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.

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December 22, 2023

Sustainability work puts numbers on chipmaking production at IEDM

Shifting to low-carbon generation for electricity would do much to cut the carbon footprint of semiconductor processes according to work shown at this year’s IEDM.

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December 18, 2023

FD-SOI processes lead to double-decker monolithic 3D

At IEDM, CEA-Leti described a process that avoids the thermal problems of implementing CMOS transistors in the metal stack using monolithic integration.

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December 6, 2023

Applied and CEA-Leti team up for novel materials R&D

Applied Materials and CEA-Leti have expanded their collaboration with the creation of a joint lab to develop materials useful for sensors, RF communications, and power devices, and with a focus on heterogeneous integration.

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December 5, 2023

Zero ASIC open sources system simulation/emulation platform

Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.

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