Tech Design Forum Briefing


Briefing Authors

Paul Dempsey

Paul Dempsey Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.

Luke Collins

Luke Collins Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.

Chris Edwards

Chris Edwards Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
September 21, 2020

Deliver RFIC reliability and performance through automation

Today’s increasingly complex and integrated RFICs pose complex verification challenges best addressed before costly simulation runs.

September 14, 2020

Aprisa team to be doubled after Mentor purchase

Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.

September 14, 2020

nVidia commits to buy Arm from Softbank

Graphics and AI specialist nVidia has been confirmed as the buyer of Arm from Softbank Vision Fund in a transaction worth up to $40bn, with the fund retaining a 10 per cent share in Arm if the deal completes.

August 27, 2020

Cloud access to emulator helps AI processor start-up prove design, win funding

Small startup gets flexible cloud access to big iron to prove a novel processor architecture quickly.

August 27, 2020

Automotive E/E design demands a multi-domain, system-led approach

Increasing complexity means that teams must leverage automation to work across disciplines, speed delivery and free room for innovation.

August 25, 2020

TSMC fills in sub-nodes as EUV gains ground

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.

August 17, 2020

Cadence uses machine learning to trim constrained-random runtimes

Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.

August 12, 2020

How to handle PCB constraints for IoT designs

An RF Laboratories engineer provides some tips and techniques in the context of the PADS Professional suite.

July 31, 2020

Open-RAN puts more focus on emulation in testing programs

Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.

July 30, 2020

Second formal check aids deadlock hunting

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.

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