Nvidia proposes split-level link for chiplet interconnect
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Agile Analog adds digital library for easier porting
Agile Analog has launched its own digital standard cell library, designed to be used in the control circuits for analog blocks that form the IP company’s main offering.
Cadence extends AI to verification data with unified database
Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
X-Fab to add 130nm SiGe with IHP deal
X-Fab is using IHP technology to add a 130nm silicon germanium process to its offering.
Module verification demands integrated DRC and LVS
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Use equivalence checking to retarget obsolete FPGA designs
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
Parasitic extraction challenges intensify for 5G
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
Cybersecurity must be built in not bolted on
Learn how one of the leading tool vendors addresses the security of its products and customer data through a ground-up cybersecurity strategy.
Intel and partners join for RISC-V development push
Intel’s Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Imperas releases RISC-V coverage library as open source
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
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