Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
Xilinx has reworked its Versal FPGA for edge-AI applications.
TSMC is developing processes for high-end automotive and RF based off its N5 and N7 families.
IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
Determining which embedded technique to adopt is more than just a question of what cores the system has.
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Arm is reworking the DesignStart scheme it introduced several years, moving it under the umbrella of the broader Flexible Access program.
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