The vendor has reworked its website and discussed more about its strategy going forward, following its rebranding from Mentor.
Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
Siemens has introduced a cloud-based DFM tool intended to bridge the gap between the electronics design and manufacturing.
Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
Arm aims to introduce a novel security model in its upcoming v9 architecture along with further extensions for AI.
Imperas Software has released a free instruction set simulator that covers the OpenHW Group’s implementations of the RISC-V processor architecture.
Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
The best paper awards at this month’s DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
At the recent Embedded World show and conference, Colin Walls of Siemens tackled the choices facing software developers working with multicore SoCs.
IRPS will use a virtual format for its March conference and will take in the reliability of emerging as well as more established technologies.
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