There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.
A technical paper originally presented at DVCon USA 2020 simplifies the creation of coverage strategies using manual, automated and verification IP components.
View All Sponsors