data center

November 12, 2019

Xilinx aims for software flow with Vitis

Xilinx has released the first version of its Vitis development environment as the company aims to capture a user base that is more used to software than hardware tools.
Article  |  Topics: Blog - Embedded  |  Tags: , , , ,   |  Organizations:
July 2, 2019

SmartDV adds verification IP for OpenCAPI data-center standard

The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
June 3, 2019

Analyst: China’s foreign EDA thirst to grow despite trade tensions

Analyst Rich Valera points to China as a major source of EDA tool growth despite short-term tensions with the US government.
May 28, 2019

Cadence expands Protium for rack-based prototyping

Cadence has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.
May 21, 2019

Achronix deploys network on chip for faster FPGAs

Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
Article  |  Topics: Blog - IP, PCB  |  Tags: , , , , , , , ,   |  Organizations:
April 4, 2019

ODSA weighs options for chiplet interconnect

An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
March 20, 2019

Microsoft offers free RTL for fast server compression

Not only has Microsoft decided to make a compression algorithm intended for data centers open source, the company the company is providing its own RTL to anyone who wants to implement it in silicon.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations: ,
March 18, 2019

PCI may provide key to OCP chiplet standard

The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.
March 6, 2019

MACOM to use GlobalFoundries 300mm SOI for PICs

MACOM has decided to use GlobalFoundries' 90nm SOI process on 300mm wafers to build higher-integration optical-switching devices for servers.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , ,   |  Organizations:
December 4, 2018

Achronix builds machine learning IP into eFPGA

Achronix has incorporated direct support for machine learning into the latest version of its eFPGA architecture.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations:

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