Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Waferscale SSDs are among the future drive architectures being explored by Kioxia, according to a keynote delivered at VLSI Symposia.
Xilinx has released the first version of its Vitis development environment as the company aims to capture a user base that is more used to software than hardware tools.
The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
Analyst Rich Valera points to China as a major source of EDA tool growth despite short-term tensions with the US government.
Cadence has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.
Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
Not only has Microsoft decided to make a compression algorithm intended for data centers open source, the company the company is providing its own RTL to anyone who wants to implement it in silicon.
The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.
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