Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.
The 63rd IEDM has issued a call for papers for its conference in San Francisco in early December and has stuck with the later deadline introduced last year.
Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab
FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
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