At IEDM, TSMC is at the top of several papers that examine how 2D materials might be put into action as successors to silicon, alongside work from a variety of institutions on power integration and thermal management.
TSMC calls for modular EDA flows and increased use of hierarchical verification to support complex 3DIC designs.
TSMC is developing processes for high-end automotive and RF based off its N5 and N7 families.
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.
TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
A Mentor-Samsung collaboration cuts the need for model-based analysis and speeds analysis runtime by as much as 20X.
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
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