Foundry

June 15, 2020

EDA in the cloud boosts DRC iterations for AMD

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Article  |  Topics: Blog Topics  |  Tags: , , , , , , , , ,   |  Organizations: , , ,
January 10, 2020

MRAM pushes speed and endurance at IEDM

IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: , , ,
December 16, 2019

Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm

Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
October 29, 2019

Foundries call off patent war

GlobalFoundries and TSMC have called off their legal battle with a wide-ranging patent cross-licensing deal.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations: ,
October 14, 2019

Integration forms highlights of upcoming IEDM

Different forms of heterogeneous integration take center stage at the IEEE International Electron Device Meeting (IEDM) in December this year.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , , ,
October 3, 2019

X-Fab expands MPW access through Europractice

Mixed-signal foundry X-Fab has expanded the range of processes that it will offer for prototyping through the Europractice service.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
August 27, 2019

GlobalFoundries takes aim at TSMC’s customers in patent action

GlobalFoundries is calling for imports of chips fabbed by TSMC into the US and Germany in multiple actions based on a list of 16 patents.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations: , , ,
August 15, 2019

Optimized DRC in the cloud

A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
July 3, 2019

How to automate pre-tape-out ESD protection verification

A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.
Article  |  Topics: Design to Silicon, Blog - EDA, - Technical Articles, Verification  |  Tags: , ,   |  Organizations: ,
June 6, 2019

Calibre scales to 4000 nodes for faster sign off in the cloud

AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors