Foundry

August 28, 2018

GlobalFoundries stops 7nm work to focus on existing processes

GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations:
July 12, 2018

With RF, power and MRAM, FD-SOI finds its role

FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations: , , ,
June 25, 2018

Node-variant FinFET tweaks try to improve cost, performance

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,
June 22, 2018

GlobalFoundries plays with metal gear in search for solid gains

At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
June 18, 2018

DAC 2018 preview: Synopsys

DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.
Article  |  Topics: Conferences  |  Tags:   |  Organizations: , , , , , ,
May 9, 2018

Motion harvester wins MEMS design contest

Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
May 4, 2018

7nm process with EUV to feature at VLSI

Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , , ,
May 2, 2018

TSMC certifies Synopsys tool flow for 7nm EUV process

New flow enables high-performance, high-integration designs.
Article  |  Topics: Blog - EDA, - Product  |  Tags: , ,   |  Organizations: ,
March 23, 2018

Layout schema generation speeds early-stage yield learning

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
December 1, 2017

X-Fab cuts flicker noise for 180nm process

X-Fab has added a process module to its wide voltage- and temperature-range 180nm mixed-signal process that supports a set of transistors with lower 1/f flicker noise.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:

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