3DIC design needs more hierarchy, TSMC says

By Chris Edwards |  No Comments  |  Posted: June 20, 2022
Topics/Categories: Blog - EDA  |  Tags: , , , ,  | Organizations:

At the recent VLSI Technology and Circuits Symposium, TSMC senior vice president of R&D Yuh-Jier Mii called for changes in design that he argued would make it easier to implement 3DIC multichip modules.

In his plenary talk, Mii argued for what he termed “modularized 3DIC design” in an environment where the number of individual dies in a package is likely to grow from single digits to double digits and that “the current design infrastructure, based on the existing 2D [design] environment, is not able to handle the enormous rise [in complexity]”.

Mii claimed the foundry has identified a number of modular EDA components that can fit into a 3DIC design stack that would cooperate to support physical design and verification, taking into account timing, power and thermal signoff. In several of these tasks, Mii pointed to greater use of design hierarchy to reduce the need to evaluate numerous corners across tens of chips, noting that static timing analysis (STA) is going to suffer disproportionately from the timing uncertainty that arises from dies in the same package occupying potentially very different process corners.

Traditionally, designers have compensated for the timing differences by adopting relatively high power interconnect protocols designed to traverse package-scale traces. With finer bump pitches being deployed, the trend to reduce the I/O delay and power overhead will make timing uncertainty harder to handle and call for a greater focus on inter-die STA. Mii proposed a hierarchical approach, with timing paths in the inter-die class being treated as a separate class. This would be used hand-in-hand with “smarter enumeration of corner combinations” to keep runtime under control. The hierarchical approach, Mii claimed, led to a doubling in runtime for 3DIC stacks compared to a 12-fold increase for flat STA across the communicating dies.

Similarly, Mii called for hierarchical thermal analysis, noting that the foundry has collaborated with EDA partners on this. “The hierarchical thermal analysis approach alleviates the tradeoff of model mesh resolution and runtime [used] in the conventional approach. Instead of using a uniform mesh to model the entire die area, this new approach can identify hotspots for more detailed analysis” and use a finer-grained mesh to analyse how heat transfers through the routing. He claimed this approach led to a ten-fold reduction in runtime with less a 2 percent difference from a golden simulation.

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