floorplanning

The flat nature of traditional IC packaging design struggles to cope with the chiplet era. Homogeneous disaggregation offers an alternative.

Get to know more on the specific benefits of shift left and how to achieve easy adoption.

Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.

The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.

Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.

Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.

Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.

Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.

Until the software is ready, it's often hard to tell when two neighbouring units on an SoC could combine to push the package past its maximum thermal point. Docea Power aims to help.