Three libraries tune speed and density on TSMC’s 3nm process

By Chris Edwards |  No Comments  |  Posted: June 3, 2021
Topics/Categories: Blog - EDA, IP  |  Tags: , , ,  | Organizations:

TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.

Expected to move to volume production in the second half of 2022, the N3 process will offer “a full node scaling benefit” compared to the previous N5 node, according to Kevin Zhang, senior vice president of business development at TSMC during the company’s annual technology symposium. Unlike Samsung, which has opted for nanosheets for its take on the 3nm generation that is expected to move into production in 2023.

In his introductory speech, CEO CC Wei said TSMC is continuing with finFETs for one more generation because they “deliver the best maturity and cost effectiveness”.

Zhang added in a meeting with journalists, “Our technology team was able to find innovative knobs to turn to tune performance. We also want to be sure to deliver this technology early with predictable timescales and schedules”.

The successor N2 is likely to be based on a nanosheet device but Zhang said “you probably want to wait for next year’s symposium for the schedule”.

The three libraries for N3 are divided in HD, HC and HPC, with the HD being the one that is expected to offer around a 60 per cent improvement in density for designs compared to N5. HPC offers a significantly smaller scaling benefit but can support higher-frequency circuits. HC lies between the two, though with a higher weighting to density rather than speed gains.

A potential issue with highly scaled finFETs is in the heat generated by the smaller transistors. TSMC has published patents that describe methods for creating micro-heatsinks onchip to prevent hotspots forming around fast-switching transistors, which may play into the performance/density tradeoff. Commenting on the scaling numbers published by the company at its symposium this week, Zhang said the density estimates for the different cell libraries were derived from real customer designs.

Yujun Li, director of high-performance computing business development at TSMC, said the three libraries for N3 can be mixed and matched on-chip so that the larger cells of HPC need only be deployed on circuits that need them.

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