Foundry

February 21, 2017

Xilinx to bring analog conversion onto finFET FPGAs

Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , , , ,   |  Organizations: ,
February 13, 2017

SPIE Advanced Lithography preview: Mentor Graphics

The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.
January 18, 2017

Wafer expansion hits the buffers

What's old is new: 200mm wafers are returning and driving shortages while 450mm fades into the distance.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: ,
December 12, 2016

IEDM explores faces of 3D monolithic integration

What will 3D integration look like? IEDM 2016 explored some of the options ranging from IoT sensors to advanced logic.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations:
October 24, 2016

Serdes deal to push copper server interconnect to 100Gbit/s

A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
September 16, 2016

GlobalFoundries ports MRAM to 22nm FD-SOI

GlobalFoundries has introduced an embedded-MRAM option for its 22nm FD-SOI process: the 22FDX platform.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations:
June 20, 2016

DTCO points to sub-10nm optimizations

DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , , ,   |  Organizations: ,
May 18, 2016

ARM completes multicore test chip on 10nm finFET

ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
April 7, 2016

SNUG 2016: Intel, TSMC, GloFo back post-finFET research at UC Berkeley

But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
February 11, 2016

SPIE Advanced Lithography Preview: Mentor Graphics

The Calibre vendor will have a strong technical presence at the leading lithography conference taking place in late February in San Jose.

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