timing closure

TSMC calls for modular EDA flows and increased use of hierarchical verification to support complex 3DIC designs.

Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.

Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.