timing closure


July 15, 2014

Cadence targets finFETs with RC extraction speedup

Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
November 12, 2013

Cadence ties IR drop into static timing analysis

Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

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