Vertical integration expands at IEDM
Vertical integration is one of the major focus areas at the upcoming International Electron Device Meeting (IEDM) early in December, both in terms of transistors and the multiple channels that will go into them.
Since being proposed by Imec several years ago, the stacked complementary FET has moved to become the most likely candidate for a viable sub-2nm process able to deliver area savings. Work is moving forward at Intel and TSMC, with the latter submitting a late-new paper that describes a design with a 48nm gate pitch that places an n-channel FET over a p-channel counterpart and which, in the experimental device, showed a greater than 90% process-survival rate.
Intel’s submission also places the n-channel over the p-channel transistor but with three nanosheets in each transistor, organised to form functional inverters, albeit with a more relaxed gate pitch of 60nm. The process used also provides backside power delivery and direct backside contacts. At the conference, the team will describe a method for effectively removing nanosheet from the devices to deal with situations where different numbers of n-channel and p-channel devices are needed in a cell.
Looking further forward, at the event, TSMC will describe work with Taiwanese research institutes to improve the performance of stacked nanosheets made from monolayer channels of molybdenum disulphide (MoS2). Experimental devices with a pair of stacked 40nm-long channels passed an on-current of around 370µA/µm at 1V with an on-off ratio of 100 million and a contact resistance of around 0.5kΩ.µm, a value close to that encountered by other work that used cryogenic temperatures to explore the resistivity of clean, defect-free interfaces. The team achieved the improved conductivity by using a C-shaped, wraparound contact to increase surface area but they point out that more work is needed to prevent the formation of defects.
Work by Samsung used oxide-based materials previously used to explore horizontal thin-film transistors to help improve the areal density of DRAMs by turning the structure on its side. The team used indium gallium zinc oxide (IGZO) to form a vertical-channel that is stacked over conventional control transistors to obtain a cell area of 4F2 versus a more common 6F2 structure. According to the researchers, the devices will be suitable for sub-10nm DRAMs and will help suppress row-hammer interference compared to a conventional planar design, largely because the active region is not shared with adjacent cells.
