How to handle PCB constraints for IoT designs
An RF Laboratories engineer provides some tips and techniques in the context of the PADS Professional suite.
RF
Parasitic extraction to guide capacitor usage in RF SoCs
A white paper details the parasitic extraction technology needed to help design high-performance RF SoCs.
GlobalFoundries stops 7nm work to focus on existing processes
GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
With RF, power and MRAM, FD-SOI finds its role
FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.
SAR-VCO combo tunes RF receiver power on 16nm
Researchers from the UC Berkeley and Intel teamed up to develop an energy-tuneable RF front-end on a digital finFET process with no need for analog process options.
FPGA powers custom RF tests on low-cost module
Slovenian startup Red Pitaya has added a front-end module and firmware to its FPGA-based StemLab board to create a customizable vector network analyzer (VNA) and RF tester.
Overcome IoT edge challenges with integrated flows
IoT edge designs are being undertaken by multi-disciplinary teams that must work within the tightest of budgets.
Webinar focuses on Eldo RF verification of Tanner-based designs
On-demand seminar explains how to exploit recently announced integration of Tanner and Eldo suites for sensor, IoT and other design types.
Spectrum analyzers aim for IoT projects
Tektronix has aimed a pair of RF instruments at the growing number of engineering teams trying to incorporate low-power wireless communications into their designs.
GlobalFoundries tunes 28nm for smaller, lower-power FD-SOI
GlobalFoundries has developed variants of the 28nm FD-SOI process that offer smaller die sizes and lower-power operation.
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