An RF Laboratories engineer provides some tips and techniques in the context of the PADS Professional suite.
A white paper details the parasitic extraction technology needed to help design high-performance RF SoCs.
GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.
Researchers from the UC Berkeley and Intel teamed up to develop an energy-tuneable RF front-end on a digital finFET process with no need for analog process options.
Slovenian startup Red Pitaya has added a front-end module and firmware to its FPGA-based StemLab board to create a customizable vector network analyzer (VNA) and RF tester.
IoT edge designs are being undertaken by multi-disciplinary teams that must work within the tightest of budgets.
On-demand seminar explains how to exploit recently announced integration of Tanner and Eldo suites for sensor, IoT and other design types.
Tektronix has aimed a pair of RF instruments at the growing number of engineering teams trying to incorporate low-power wireless communications into their designs.
GlobalFoundries has developed variants of the 28nm FD-SOI process that offer smaller die sizes and lower-power operation.
View All Sponsors