Putting chiplet design on the ‘smart path’
The flat nature of traditional IC packaging design struggles to cope with the chiplet era. Homogeneous disaggregation offers an alternative.
PPA
Cadence mixes know-how and AI to bridge RTL gap
The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
Mediatek extends big.LITTLE strategy with ‘tri-cluster’ smartphone CPU
Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
Cadence signs with ARM for core optimizations
Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.
Synopsys launches single kit to optimize IP across PPA
Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.