PPA


June 24, 2015

Mediatek extends big.LITTLE strategy with ‘tri-cluster’ smartphone CPU

Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
Article  |  Topics: Conferences, Blog - IP, - Verification  |  Tags: , , , , , ,
May 20, 2014

Cadence signs with ARM for core optimizations

Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , , ,   |  Organizations: ,
June 14, 2013

Synopsys launches single kit to optimize IP across PPA

Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
Article  |  Topics: Digital/analog implementation, Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,

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