Foundry

A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.

A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.

AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.

Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.

An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.

The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.

It's been a long time coming, but silicon photonics is now entering commercial design for networking and grabbing attention in autonomous driving and sensors.

Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.

Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.