Curvilinear layout looks to wider adoption with mask speedups
Curvilinear design is beginning to look as though it is finally here to stay following a group of supply-chain providers deciding to partner with Nvidia on its plans to broaden the types of mask-making algorithm that can be handed off to its GPUs.
At Nvidia’s Spring GTC, the GPU maker disclosed that it had been working on an acceleration library for optical proximity correction (OPC) and inverse lithography, which has won support from ASML, Synopsys, and TSMC.
Providing acceleration for these functions is far from new. Mask-software specialist D2S has built GPU-based systems for years. And when Mentor Graphics (now part of Siemens) signed an agreement with IBM for computational- and inverse-lithography technology almost 15 years ago, acceleration using arrays of IBM’s Cell processors was considered as a likely option before general-purpose GPU acceleration became an accepted approach for speeding up numerically intensive software.
The area that Nvidia’s initial suite of algorithms in cuLitho focuses on, however, look to be operations that have not traditionally been considered as viable on GPUs. For its software, D2S used a pixel-oriented approach rather than one that analyzes the straight edges provided by back-end EDA tools. This pixel-oriented approach was recommended by Nvidia’s advanced-technology group vice president, Vivek Singh, in a 2008 paper when he was at Intel. Converting the desired target layout to pixels rather than processing straight-line shapes and edges provides a good deal more flexibility in what is possible in terms of building masks that deliver more robust on-chip results. It is also a more natural fit for inverse lithography, in which the desired target is used to generate a mask image that often bears little similarity to even an OPC-processed layout.
However, the functions in cuLitho highlighted at GTC by Singh tend to focus on shapes and edges: parallelising operations built by users of the library that look for overlaps and search for patterns. These, Nvidia expects will be used on top of functions for GPUs which are already being used.
“The imaging part of computational lithography can be represented by convolutions, or matrix multiplications, which are inherently amenable to parallelisation,” Singh explains. “All the remaining operations, however, have historically proven to be bigger bottlenecks, and this has limited the acceleration of end-to-end OPC tools.”
Shapes and pixels
Aki Fujimura, chairman and CEO of D2S, notes, “They’re anticipating what kinds of library components would be useful for people to be able to do a good job on GPUs from the outset and make it easier for companies to move their code to being CPU to GPU-based.
“The majority of customers are CPU-based. And when they do GPU acceleration, the right thing for them to do is to stay in edge-based for the moment. But we take a different approach.”
Though the emphasis in the initial cuLitho release appears to be on speeding up the production of masks that rely more on conventional shape-based OPC rather than full inverse lithography, at GTC both Singh and Nvidia president and CEO Jensen Huang pointed to cuLitho being the basis of the company’s aims to support one of the spinoffs of inverse lithography: the ability to image curvilinear patterns as well as traditional Manhattan layouts.
Singh used a recent paper from TSMC as an example. “Curvilinear masks deliver a superior process window. They show that compared to the standard OPC, the curvilinear [inverse lithography technology] gives about 2x the depth of focus or depth of field.”
Though memory makers such as Micron have made warmer noises about the value of curvilinear patterns, and can devote more time to creating custom shapes for cells that repeat billions of times across a single chip layout, Fujimura claims the combination of EUV lithography and multibeam mask-writing tools that are better able to support the approach is pushing those at the leading edge to adopt the same principles. According to recent statistics, multibeam writers are used almost exclusively for EUV mask production. The traditional variable shaped beam (VSB) mask writers, which are optimized more for Manhattan patterns with less aggressive OPC, remain in place for 198nm lithography and older technologies.
“In 2022, the big transformation happened. In 2021 curvilinear masks were being talked about as a good thing, that it’s good for quality. Then it became a done deal. Everybody’s going to do curvilinear masks for EUV, specifically for EUV at the 2nm node and below. They don’t do it now. But it’s quite a transition in only two or three years. And it’s pretty much like, if you don’t do it, you’re behind,” Fujimura says.
Fujimura reckons the most likely target in logic-dominated layouts for curvilinear shapes is rather than the base transistor layers and lower-level metal layers, which tend to favor 1D layouts because these provide greater packing density, chipmakers will focus on the local routing found in the middle-of-line layers, and which is used primarily for intra-cell connections. As with memories, the repeated use of a small number of common cells across the chip may help overcome some of the EDA tool-related issues that result from moving from pure Manhattan designs to more curved layouts.
In principle, the curvilinear approach could be adopted in older process nodes to eke out a little more process window. But Fujimura notes that fab operators dislike making major changes once a process has matured: “Once something works, better is different. And different is bad.”
However, the growing use of silicon photonics, where curved shapes are essential, may see greater adoption of inverse lithography techniques to improve results at the cost of longer VSB-based mask-creation times. And newer specialist processes for IoT or power applications that use older process equipment may also benefit over time.
The world of Manhattan design may finally be giving some way to the apparent process-yield advantages of curvilinear layouts, helped on the way by speedups in inverse lithography.
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