Chipmaker

Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.

The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.

The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.

Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.

Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.

X-Fab is using IHP technology to add a 130nm silicon germanium process to its offering.

Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.

Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.

Teledyne e2v has demonstrated a prototype optical link that the company believes could replace electrical signaling for remote RF heads.

As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.