Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.
Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
DAC and the RISC-V Summit will colocate at Moscone West in December, along with Semicon West.
Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.
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