RISC-V International


November 3, 2023

Codasip pips Arm to commercial CHERI with RISC-V version

Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.
April 17, 2023

Semidynamics pushes configurability on RISC-V core for HPC

Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: ,
August 3, 2022

Imperas releases RISC-V coverage library as open source

Imperas Software has published an open-source functional-coverage library for RISC-V cores.
June 28, 2022

Aachen spinout claims fastest RISC-V simulator

MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
August 2, 2021

DAC and RISC-V move in together at Moscone in December

DAC and the RISC-V Summit will colocate at Moscone West in December, along with Semicon West.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
November 27, 2020

RISC-V in nearly a quarter of designs (Wilson Functional Verification 2020 – Part One)

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.

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