Chipmaker

April 28, 2022

Go inside proposals for common chiplet models

Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
March 23, 2022

Nvidia open to chiplet standards

Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
March 4, 2022

Verification engineers look to better skills to beat schedules

A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , ,
February 8, 2022

Arm aims for IPO as Nvidia calls off its bid

Nvidia has decided to give up on acquiring Arm from SoftBank. The IP provider will now aim for an IPO by the end of March 2023.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations: ,
December 31, 2021

AMD moves gradually into 3D integration

At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations:
December 9, 2021

Flexible hybrid electronics: Making an emerging tech happen with PDKs and reference designs

FHE use-cases are evolving and the NextFlex consortium is looking to smooth their path with a strategy, PDKs and reference modules.
December 6, 2021

DAC 2021 preview: Breker Verification Systems

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
November 23, 2021

DAC 2021 Preview: Siemens EDA

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
November 5, 2021

UK consortium starts work on cryogenic CMOS

A £6.5m grant will fund the development of memories and other IP to improve the control of qubits in quantum computers.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
October 28, 2021

Emulation’s scheduling challenge

Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: , , ,

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