Chipmaker

Alphawave Semi has collaborated with Arm on the development of an advanced compute chiplet based on Arm’s Neoverse compute subsystems.

This year’s ECTC, held at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.

The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.

Arm has launched what the company claims is its highest-performance and most-efficient AI accelerator.

Arm is working with Cadence and Siemens on separate projects to support its plans in the SDV space.

Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.

Arm has added machine-learning extensions and pointer-security instructions to its latest Cortex-M series core.

Siemens has made its PAVE360 automotive digital-twin software available on AWS, with the ability to access fast Arm models on the same cloud.

Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.

X-Fab has made it possible to put galvanic isolation based on capacitive coupling directly into chips made on its XA035 process.