Arm has added machine-learning extensions and pointer-security instructions to its latest Cortex-M series core.
Siemens has made its PAVE360 automotive digital-twin software available on AWS, with the ability to access fast Arm models on the same cloud.
Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.
X-Fab has made it possible to put galvanic isolation based on capacitive coupling directly into chips made on its XA035 process.
SureCore and Intrinsic have teamed up to provide a way to implement resistive random-access memory as an SoC-embeddable technology.
From tutorials to technical papers to special 'diamond' sessions, Tessent features large at ITC 2023.
Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.
DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.
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