Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Breker's presence at next week's Design Automation Conference (DAC) will emphasize a new collaboration around the RISC-V platform.
Axiomise founder and formal expert Ashish Darbari will present across multiple events at DAC in San Francisco next week.
MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.
Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
DAC and the RISC-V Summit will colocate at Moscone West in December, along with Semicon West.
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