Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Breker's presence at next week's Design Automation Conference (DAC) will emphasize a new collaboration around the RISC-V platform.
Axiomise founder and formal expert Ashish Darbari will present across multiple events at DAC in San Francisco next week.
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