RISC-V

June 28, 2022

Aachen spinout claims fastest RISC-V simulator

MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
May 25, 2022

Siemens brings ReadyStart RTOS to RISC-V

Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
Article  |  Topics: Blog - Embedded  |  Tags: , , , ,   |  Organizations:
December 6, 2021

Imperas pulls together tools for RISC-V verification

Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:
December 6, 2021

DAC 2021 preview: Breker Verification Systems

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
August 2, 2021

DAC and RISC-V move in together at Moscone in December

DAC and the RISC-V Summit will colocate at Moscone West in December, along with Semicon West.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
April 16, 2021

Siemens buys formal start-up OneSpin

The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
March 29, 2021

OpenHW gets free simulator from Imperas

Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , ,   |  Organizations: ,
February 15, 2021

Getting a RISC-V embedded toolchain in place

A new white paper reviews the history of the open-source platform and provides guidance on best practice development for embedded.
Article  |  Topics: Blog - Embedded, - Next Generation Design, Standards  |  Tags: , ,   |  Organizations: ,
December 1, 2020

Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
November 27, 2020

RISC-V in nearly a quarter of designs (Wilson Functional Verification 2020 – Part One)

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.

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