December 5, 2023
Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.
August 31, 2022
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
October 28, 2021
Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
April 19, 2021
Siemens's expansion of the Veloce hardware-assisted verification platform delivers on one of its current mission statements.
April 6, 2021
Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
March 26, 2021
Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
April 2, 2019
RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.
February 27, 2017
Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
June 3, 2015
Arduino Due shield interface makes adding peripherals to a Cortus-based SoC prototype easier.
September 29, 2014
Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs