Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
Siemens's expansion of the Veloce hardware-assisted verification platform delivers on one of its current mission statements.
Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.
Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
Arduino Due shield interface makes adding peripherals to a Cortus-based SoC prototype easier.
Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.
View All Sponsors